Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
As technology has progressed, the demand for smaller semiconductor devices with improved performance has increased. A move is being made away from the traditional materials used in the past in semiconductor device designs, to meet these demands. For example, in the past, aluminum and aluminum alloys were most often used as a conductive material for conductive lines and vias in metallization structures, and silicon dioxide was used as an insulator between conductive lines and vias. However, as semiconductor devices have been scaled down in size, conductive features made from these materials have exhibited an increase in propagation delay.
For example, as minimum feature size decreases, RC time delay begins to limit the propagation delay of integrated circuits. RC time delay refers to the product of the metal resistance (R) and the dielectric capacitance (C). To reduce the RC time delay, low dielectric constant materials are being used as insulating materials, and there is a switch being made to the use of copper for interconnect materials, rather than aluminum.
One advantage of switching from aluminum to copper for semiconductor device interconnects is increased speed. Because the use of copper decreases the RC time delay due to the decreased resistivity of copper, devices can operate faster. There are also other advantages of switching to copper interconnects. For example, copper has a lower resistivity and increased electromigration resistance compared to aluminum. The reduced resistivity of copper results in the ability to manufacture thinner conductive lines, reducing the sidewall capacitance of the conductive lines. Also, because copper has improved electromigration resistance, higher current densities may be used.
RC time delays for interconnects can severely limit microprocessor clock speed. This limitation can be overcome by switching from aluminum to copper, and can be further improved by the use of copper in conjunction with low-k dielectric materials. Combining copper interconnects with low-k dielectric materials increases interconnect speed by reducing the RC time delay, for example.
However, there are some challenges in using copper for an interconnect material. For example, copper oxidizes at a relatively low temperature compared to aluminum, and the oxide formed on copper is not a high quality oxide, as is aluminum oxide. Copper does not form a self-passivating oxide on its surface, as aluminum does. Rather, portions of the copper interconnect remain exposed and are thus more susceptible to corrosion. It is difficult to directly etch copper, e.g., in a subtractive etch process, and thus, copper interconnects are often formed using damascene processes rather than by direct etching. A damascene process is one in which a dielectric material is deposited on a wafer, and then the dielectric material is patterned with the conductive line pattern. The conductive line pattern typically comprises a plurality of trenches, for example. The trenches are then filled in with conductive material, and a chemical-mechanical polish (CMP) process is used to remove the excess conductive material from the top surface of the dielectric material. The conductive material remaining within the dielectric material comprises the conductive lines.
Damascene processes are typically either single or dual damascene. In a single damascene process, one metal layer is formed at a time. For example, the insulating layer is patterned and then filled with metal, and a CMP process is used to form a single metal layer. In a dual damascene process, two adjacent horizontal insulating layers are patterned, e.g., using two lithography patterns in the two insulating layers or a single insulating layer that are filled with metal, and a CMP process is used to remove excess conductive material and form patterned conductive material in the insulating layers. For example, the patterns may comprise conductive lines in one insulating layer portion, and vias in the underlying insulating layer portion. The vias may connect the conductive lines to devices or interconnect layers that reside in the underlying insulating layer. Thus, in a dual damascene process, conductor and via trenches are filled in one fill step.
Because copper oxidizes easily, it may be desirable to treat the top surface of copper conductive lines, e.g., with a passivation layer. However, it can be challenging to form a passivation layer that is uniform over the entire surface of a semiconductor workpiece.
Thus, what are needed in the art are improved methods of forming passivation layers over conductive features of semiconductor devices.